1. Technical Field
This invention relates in general to integrated circuit (IC) modules, such as multi-chip modules (MCMs), Single In-Line Memory Modules (SIMMs), and Dual In-Line Memory Modules (DIMMs). More specifically, this invention relates to a device and method for buffering clock and other input signals received by IC modules.
2. State of the Art
As shown in FIG. 1, a typical IC module 10 includes a set of IC devices 12 that communicates with external electronic devices (not shown) through a set of input/output (I/O) pins 14. Each of the IC devices 12 has characteristic high and low voltage xe2x80x9ctripxe2x80x9d points VIH and VIL at which each device 12 will register, respectively, high and low states in an input signal. In addition, each of the IC devices 12 has characteristic minimum xe2x80x9csetupxe2x80x9d and xe2x80x9choldxe2x80x9d times that characterize required minimum timing relationships between certain input signals.
In some instances, amplitude fluctuations during high-to-low or low-to-high transitions in input signals received by the IC module 10 (e.g., clock signals, Row Address Strobe (RAS), Column Address Strobe (CAS), Output Enable (OE), and Write Enable (WE)), in combination with a relatively high trip point VIH or a relatively low trip point VIL in an IC device 12, can cause the IC module 10 to fail during testing as a result of a failure of the device 12 to register a transition in one of these input signals. In other instances, the same fluctuations experienced by an IC device 12 that has a relatively large minimum setup or hold time can vary the timing relationships between certain input signals enough to also cause the IC module 10 to fail during testing. In both instances, the failing IC module 10 is typically repaired or scrapped, thereby reducing the yield and increasing the overall costs associated with manufacturing modules such as the IC module 10.
Accordingly, it would be desirable to have a device and method for IC modules that reduce or eliminate these amplitude fluctuations in input signals provided to the modules in order to improve their yield and reduce manufacturing costs.
An integrated circuit (IC) module in accordance with this invention includes a module terminal (e.g., an input/output (I/O) pin) that receives a signal (e.g., a clock). A buffering circuit in a buffering IC of the IC module then buffers the signal, and an IC device (e.g., a DRAM) in the IC module then receives and uses the buffered signal. As a result of the buffering, the signal may, for example, be delayed slightly, have improved rise and fall times, and have reduced amplitude fluctuations, all of which may contribute to improved setup and hold times when the buffered signal is received and used by the IC device. The improved setup and hold times may, in turn, lead to improved yields (because more IC modules pass testing) and reduced manufacturing costs.
In other embodiments of this invention, the IC module described above is embodied in a SIMM, a DIMM, an MCM, or an electronic system.
In a further embodiment of this invention, a signal in an IC module is prepared for use by an IC device of the IC module. The signal is initially received at the IC module (e.g., at an I/O pin of the IC module). A buffering circuit in a buffering IC provided in the IC module then buffers the signal, and the buffered signal is then conducted to the IC device for its use.
In still another embodiment, an IC module is manufactured using an IC module substrate that has multiple module terminals (e.g., I/O pins) on its surface. Multiple IC devices are mounted on the surface of the IC module substrate, along with a buffering IC that includes a buffering circuit. The buffering circuit is then electrically interposed between one of the module terminals and one of the IC devices so a signal received at the module terminal is buffered by the buffering circuit before reaching the IC device.